Enhanced Fault-Tolerant Data Latches for Deep Submicron CMOS

CMOS data latches used in critical applications must be immune to soft errors such as single event upsets. Existing designs protect the stored data against errors in the internal nodes, but may be vulnerable to transient faults in the control and data lines. The problem becomes more severe as feature sizes decrease. In this paper, we enhance the Dual Interlocked Storage Cell (DICE) to withstand soft errors at any node. We expand our scheme to encompass five fault-tolerant memory cells: one optimized for pipeline latches, and the others for SRAM. The designs have been verified through extensive layout simulations in 180-nm CMOS. Compared to the original DICE, the proposed cells can withstand a broader class of transient faults, but consume more energy during read and write operations. We explore the tradeoff between energy consumption and the number of redundant control lines required.